发明名称 DYNAMIC TYPE RAM
摘要 PURPOSE:To stabilize an operation by continuously supplying a half precharge level to the complementary data line of the memory array of one non-selected side by a level conpensating circuit even when, a continuous access like a static column mode or a page mode is carried out to the other memory array. CONSTITUTION:The data line of a memory array MARY-L, MARY-R in which a word line is not selected is brought into a floating condition, thereby, in order to prevent is precharge level from level changing by a coupling or a leak current, a level compensating circuit is provided. Namely, to complementary data lines D, inverse of D of a left side memory array MARY-L, a dividing voltage of Vcc/2 formed by potential dividing resistances R1, R2 is supplied through transmitting gates MOSFET Q1-Q4 controlled by a timing signal of inverse of phiL. Also in the right side memory array MARY-R, a similar level compensating circuit is provided.
申请公布号 JPS61217992(A) 申请公布日期 1986.09.27
申请号 JP19850058405 申请日期 1985.03.25
申请人 HITACHI CHIYOU LSI ENG KK;HITACHI LTD 发明人 KOYAMA YOSHIHISA
分类号 G11C11/409;G11C11/34;G11C11/401 主分类号 G11C11/409
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