发明名称 PSEUDO ERROR SIGNAL GENERATION CIRCUIT
摘要 PURPOSE:To perform the desired circuit test accurately by altering data to be set for an electronic circuit to be tested according to the output of the set signal from a latch circuit to set data containing a pseudo signal. CONSTITUTION:The input 33 before the time t1 is set on a register 30 at the time t2 on a set clock 35 and errors in the contents thereof is detected with a checking circuit 32 at the check timing to the time t3. Then, when testing a register 30, a signal for setting a latch 38 is provided to a line 39 at an appropriate time before the time t1 to set the output of a latch 38 at ''1''. The output 37 is altered to generate a pseudo error in the input of the register 30 at a gate circuit 36. Therefore, an erroneous data is set for the register 30 at the time t2 and when the checking circuit 32 is normal, an error display signal is outputted. The latch 38 is reset by the clock 35 at the time t2 simultaneously with the setting of the register 30. Following the subsequent clock 35, the input 33 is set without alteration.
申请公布号 JPS60213874(A) 申请公布日期 1985.10.26
申请号 JP19840070397 申请日期 1984.04.09
申请人 FUJITSU KK 发明人 TOYOKI NORIYUKI
分类号 G01R31/28;G01R31/317;G06F11/26 主分类号 G01R31/28
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