发明名称 PARITY CHECK SYSTEM FOR STORED DATA IN MEMORY DEVICE
摘要 PURPOSE:To reduce the amount of hardware of a memory for parity bits by adding a parity adding circuit and a parity checking circuit and utilizing all bits of the parity bit memory effectively. CONSTITUTION:When data are written in memory devices 1-0-1-7 for data storage, the parity adding circuit 4 finds the correspondence among an address of a corresponding memory, an address of the memory device for parity bits, and the bit position in the address and writes a parity bit in the memory device 2 for parity bits. When data is read out, the parity checking circuit 3 selects a parity bit corresponding to an address of a corresponding memory for data storage from the parity-bit memory 2 and makes a parity check on the data read out of the memory for the data storage.
申请公布号 JPS61213944(A) 申请公布日期 1986.09.22
申请号 JP19850053286 申请日期 1985.03.19
申请人 NEC CORP 发明人 KIKUKAWA SHOICHI
分类号 G06F11/10;G06F11/08;G06F12/16 主分类号 G06F11/10
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