| 摘要 |
PURPOSE:To attain to shorten a processing time, by performing skew correction processing by hardware while performing the processing of the same number of channels as coincidence detection circuits. CONSTITUTION:When a start pulse ST is inputted, coincidence detecting operation is started The clock pulse CK0 of a variable delay circuit 10 is compared with a reference clock pulse CKs by a comparator 12 and a coincidence detection circuit 14 checks whether both pulses are in a coincidence state and, at the time of non- coincidence, a pulse CT is sent out. The value of a counter 16 increases or decreases one at a time at every input of the pulse CT and, as a result, the delay time of the circuit 10 increases or decreases by unit quantity. Hereinafter, in the same way, the pulse CT is successively sent out from the circuit 14 during a time when the result of comparison is non-coincidence and the counter 16 successively increases or decreases and the delay time of the circuit 10 is successively increased or decreased. When the phase of the pulse CK0 coincides with that of the pulse CKs, the circuit 14 suppresses the feed-out of the pulse CT and the delay time of the circuit 10 is fixed to the length determined by the value of the counter 16 and a corrected pulse CK0 is obtained. Skew correction processing is conducted in parallel by a correction circuit 8 and a processing time is shortened. |
