发明名称 EEPROM margin testing design
摘要 A circuitry and method of testing programmable, variable threshold memory cells by applying a variable voltage above a normal read voltage to the control gate of a high threshold cell to determine the actual high threshold value and applying zero voltage to the control gate of a low threshold cell to determine if the low threshold is of the opposite polarity of the high threshold.
申请公布号 US4612630(A) 申请公布日期 1986.09.16
申请号 US19840635218 申请日期 1984.07.27
申请人 HARRIS CORPORATION 发明人 ROSIER, BRIAN K.
分类号 G11C5/14;G11C16/12;G11C16/34;G11C29/50;(IPC1-7):G11C11/40 主分类号 G11C5/14
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