| 摘要 |
In a data processing system (10) a CPU (22) is connected via a bus (20) to at least one slave module (24; 26; 28; 32; 36), which is supplying an operation acknowledge signal within a given time period after receipt of a command. Bus time out means determines whether the operation acknowledge signal is back in time.
<??>A memory mapping device coupled between CPU (22) address lines and the bus (20) generates a greater number of bus line signals consisting of addresses and an enabling code for selecting on and off board memory devices. Further count signals generated are placing the microprocessor (22) into various waiting states.
<??>Improved prioritized bus communication is provided by a vectored interrupt scheme.
<??>Having a plurality of distributed CPU's (22; 24), interprocessor interrupt communication is controlled by way of a pair of commonly accessible storage devices. The invention is advantageously utilized in an emulator processor (24). |
