| 摘要 |
<p>PURPOSE:To execute a parallel operation of plural arithmetic units which is synchronized with a clock signal of a high frequency, by executing exactly the synchronization, even if there is variance of a characteristic between the arithmetic units. CONSTITUTION:In case it is shown that an output signal the inverse of M from a phase difference/synchronization detecting circuit 4 is synchronized, a clock signal from a clock pulse selecting circuit 5 is switched from a frequency-divided clock pulse CLK' to a regular clock pulse CLK by a switching circuit 52. In the initial stage for executing a synchronization, the synchronization is executed by using a frequency-divided clock signal divided a regular clock signal. Even if variance of an operation stop exists between arithmetic units, since its value is fixed, the variance becomes small relatively at the time of synchronization by lowering a frequency of the clock signal, and the synchronization can be executed exactly.</p> |
