| 摘要 |
<p>PURPOSE:To read out contents of a memory cell of a single bit line without requiring a comparison voltage source circuit by setting drains of the fourth P and N-channel MOS transistors (TRs) to a high potential or a low potential in accordance with the potential of the gate of the first N-channel MOS TR. CONSTITUTION:If input terminals W and S1 are set to the high level (VDD) when write on a TR Q1 is not performed, the TR Q1 is turned on, and a ratio circuit consisting of TRs Q1, Q2, and Q3 is formed between a power supply terminal VDD and the earth point, and the potential of a bit line BL and the gate potential of a TR Q6 are lower than a potential (VDD-VTN), and an output terminal OUT goes to the high level (VDD). VTN is the threshold voltage of the TR Q3. When write on the TR Q1 is performed, gate potentials of TRs Q6 and Q7 are the same potential (VDD-VTN). An output point 2 is set to the high level (VDD), and the output terminal OUT is set to the low level.</p> |
