| 摘要 |
PURPOSE:To control integrally plural aces forms by converting the external register of a processor to a memory to a memory map,and executing an access between each of a control storage centering around the processor and a register being under the processor, by using one bus. CONSTITUTION:This system is provided with a means for handling the resisters 43, 44 in sub-controlling circuits 5, 6, as memory mapped registers, and also executing the priority control of an access generated between each of a main processor 3, a control storage 1 and the sub-controlling circuits 5, 6, a means 32 for informing the result of the priority control to the main processor and the sub-controlling circuits 5, 6, and a means by which the main processor 3 or the sub-controlling circuits 5, 6 only which receives the advice can send out an address to an internal bus 10. In this way, an efficient and general DMA controlling system of executing integrally the priority control of three accesses generated at random between each of the control storage, the main processor and the sub-controlling circuit, by using the common bus 10 is realized. |
