| 摘要 |
PURPOSE:To shorten the data transfer time by storing data simultaneously into >=2 input/output memories from a CPU just with a single input/output write pulse. CONSTITUTION:The simultaneous transfer command delivered from a CPU is stored in an FF circuit 1 in order to store simultaneously data into plural I/O devices. While a special device address command is stored in an FF circuit 8 in order to designate the common address to those I/O devices. When the circuit 1 is set, a gate 3 secures an OR between the external and internal acknowledge signals of each input/output memory. A control circuit 6 controls the input/output memory address by the signal of the gate 3.
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