| 摘要 |
The circuit can maintain a high level of a sampled signal on an output node O11 without decay in level. When the input level sampled by Q13 rises, complementary output nodes N11 and N12 of a delay circuit B1 initially remain at "1" and "0" and a capacitor C11 charges through Q11. When N12 switches to "1" after the delay, a node N13 goes more positive than VDD and turns a transistor switch Q12 hard on to connect VDD to 011. In other embodiments the delay circuit drives the transistor switch through a bootstrap circuit. |
