| 摘要 |
PURPOSE:To manufacture a highly integrated, high-speed semiconductor device, by readily forming lead-out wiring for source and drain regions when elements are miniaturized, and reducing the ratio of the source and drain regions occupying an element region. CONSTITUTION:A field oxide film 42 is formed on the surface of a P-type Si substrate 41. A gate electrode 45 comprising polycrystalline Si is formed on an element region 43 surrounded by the film 42 through a gate oxide film 44. An Si oxide film 48 is formed on the side wall of the electrode 45 by an etching method. W layers 491 and 492 are formed on the side wall of the electrode 45 by sputter etching. Then a W layer 50 is deposited on the entire surface. Low-viscosity resist 51 is applied. The W layer 50 on the electrode is removed by etch back. W layers 501 and 502, which are connected to the layers 491 and 492, are formed by photoetching. A CVD Si oxide film 52 and BPSG film 53 are formed thereon. Then contact holes 54 and 54 are provided and wirings 55 and 55 are connected. Thus the work is finished.
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