| 摘要 |
PURPOSE:To protect transfer control information from being destroyed by providing a transfer control information storage section having a storage capacity storing plural sets of the transfer control information so as to reduce timewise loss in transferring plural data blocks. CONSTITUTION:A CPU 10 outputs sequentially plural sets of transfer control information to a DMA control circuit 50 at first and outputs a device address. The DMA control circuit 50 uses an internal register 51 to store the plural sets of transfer control information outputted from the CPU 10 and having a memory address and a transferred word number as one set in the order of their generations and uses a register 52 to store the device address. Then the CPU 10 starts the DMA control circuit 50, which reads the data stored at first in the register 51. When the data transfer of one block is finished, the DMA control circuit 50 reads the data stored in the register 51 again. Thus, the data transfer control is executed continuously until the information stored in the register 51 is lost. |
