发明名称 TESTING DEVICE FOR INTEGRATED CIRCUIT AND ITS USING METHOD
摘要 PURPOSE:To detect easily and with a high accuracy whether a fault exists or not, and its existence part by coupling an electron beam testing device to a CAD system on an electronic computer. CONSTITUTION:A design data of a measuring object integrated circuit DUT is generated by a CAD system. Subsequently, by a measuring logical map generating program 16, a two-dimensional analog image signal is inputted by a prescribed timing through an image binary-coding circuit 5, and an image signal on each lattice point is converted to a logical value of '1' or '0', by which a measuring logical map for showing a two-dimensional distribution of an obtained measuring logical value is generated. Next, by a design map generating program 14, a design logical map is generated from wiring graphic information of DUT and a logical expected value of each wiring. Thereafter, both logical maps are compared and collated by a logical map collating program. In this way, the existence of a fault can be detected by a wiring unit.
申请公布号 JPS61198069(A) 申请公布日期 1986.09.02
申请号 JP19850039897 申请日期 1985.02.28
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 TAMAMA AKIO;KUJI NORIO
分类号 G01R31/28;G01R31/305 主分类号 G01R31/28
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