| 摘要 |
PURPOSE:To quicken the inter-processor communciation instruction processing by applying interlock between processors so as to reduce the hardware of processors and to simplify the firmware in issuing the inter-processor communciation instruction. CONSTITUTION:When a TEST and SET instruction is executed, a processor 21 decides whether or not an FF 34 is set already depending on the signal state of a specific line on a data line of a system bus 26. When the FF 34 is set already, the processor 21 withdraws the issue of the inter-processor communication instruction while it is regarded that other processor issues the said instruction or is going to issue it. On the other hand, when the FF 34 is reset, it is regarded that the right of issue of the said instruction is given, the processor 21 issues the inter-processor communication instruction to a processor 22. When a series of processings is finished, the processor 21 executed a reset instruction resetting the FF 34. |
