发明名称 CHARGING CIRCUIT FOR BIT LINE
摘要 PURPOSE:To reduce the occurrence of power source noises during bit line charging and to prevent an internal circuit from malfunctioning by providing a resistance between the gate electrode of a transistor (TR) for bit line charging and an internal signal which controls the charging. CONSTITUTION:The resistance R1 is interposed between the internal signal PHI1 and gate electrodes of TRs 1, 2... for bit line charging. A capacitor C1 is the capacity that wiring (a) for the gate electrodes has, but a capacity may be provided specially. Consequently, the internal signal PHI1 has its rising made gentle by the time constant determined by the resistance R and capacitor C1 and is inputted to the gate electrodes of the TRs 1, 2.... Then when the value of the resistance R1 is set sufficiently large, the potential of the wiring (a) for the gate electrode rises with a large time constant regardless of the rising time of the internal time PHI1. Consequently, bit lines are charged slowly. Less noises appear on a power source line during bit line charging.
申请公布号 JPS61194698(A) 申请公布日期 1986.08.29
申请号 JP19850033933 申请日期 1985.02.22
申请人 TOSHIBA CORP 发明人 SUZUKI KIMINOBU;TODA HARUKI
分类号 G11C11/409;G11C11/34;G11C11/407 主分类号 G11C11/409
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