发明名称 FLOATING POINT ARITHMETIC PROCESSING UNIT
摘要 PURPOSE:To attain an n-th power arithmetic of a floating point at a high speed without using a complicated control circuit by using a ROM for calculation of a mantissa part and then the carries or shifts for calculation of an exponent part respectively. CONSTITUTION:An exponent part 30 has the 8-bit length of e7-e0, and a mantissa part 40 has the 22-bit length of m21-m0 respectively. When a square operation is performed with an arithmetic processor having said parts 30 and 40 having such bit lengths, the number of digits of an effective numeric character is logically limited at maximum 7 for the part 30 of the input data on the floating decimal points and at maximum 11 for the part 40 respectively. A ROM of the 23-bit output is prepared for a case where the effective numeric character has an overflow due to a squaring operation. Then the overflow information is delivered to the 23rd bit. The exponent arithmetic part sets the lowest bit of the part 30 at '1' when said overflow bit is equal to '1'. Thus the square arithmetic processing is possible at a high speed.
申请公布号 JPS61195425(A) 申请公布日期 1986.08.29
申请号 JP19850035242 申请日期 1985.02.26
申请人 CANON INC 发明人 HARUHARA IZURU
分类号 G06F7/00;G06F1/03;G06F7/552;G06F7/76 主分类号 G06F7/00
代理机构 代理人
主权项
地址