| 摘要 |
PURPOSE:To decrease the impedance of power line, absorb the potential variation, reduce the potential fluctuation of power line, and stabilize the performance, by connecting the electrostatic capacity caused by the P-N junction of virgin cells on the logic cell column to the power line with the gate array. CONSTITUTION:The drain and the source of each of the P-channel transistor 1 and the N-channel transistor 2 are connected to the power source VDD and VSS, respectively. The diffusion regions of the drain and the source which constitute the P-N junction with the substrate behave as a capacitance connected in parallel to the power line, and absorb the potential variation of power line. On the logic cell column, an example is illustrated as an embodiment. In the diagram, the basic cell 7, the macro cell 8, the power lines 9 and 10 of VDD and VSS are shown. At the time of aluminum wiring, the virgin basic cells are connected to the power line, with the contact holes 11 connecting the virgin basic cells with the power line, the contacted holes 12 connecting the metal wires with each other, and the wire grid mesh 13 for design use.
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