| 摘要 |
PURPOSE:To ensure dammy processing of a successive command without stopping an arithmatic unit when the order of vector data access is not assured between linked commands by setting a flag for each bank of a vector register. CONSTITUTION:A write address of a leading command in an address register 1-1 and a read address of the successive command in an address register 3-0 are compared in a coincidence circuit 5, which outputs 1 in the event of coincidence and 0 in the event of mismatch. When the circuit 5 outputs 0, an inverter 7 inverts 0 to 1 and a read-out valid flag 4-0 is set to 'on' through an OR circuit 8. Although the write address of the leading command and the read address of the successive command coincide, the flag 4-0 is set either to 'on' or 'off' according to an on-off state of a write valid flag 2-1. Thus, when the order of access can not be assured, the dammy processing of the successive commandtion can be performed. |
