| 摘要 |
PURPOSE:To make the high-speed application of the information read operation, by detecting a back edge of a write pulse and recovering a write signal given to a common complementary data line. CONSTITUTION:A write pulse -(WE.CS) is reverted and delayed through the CMOS inverter circuits IV4-IV10, and this delay signal and the write pulse are input into a CMOS NAND gate circuit constituted by the FETQ40-43. In a back edge when the write pulse is changed from 'L' to 'H' by this, only in the portion of the delay time set a detection signal phi that possesses a pulse width of 'H' is formed, transmitted to the switches Q35 and Q36 through a CMOS circuit and an output circuit composed of a bipolar transistor, and a voltage VCD from a power circuit is transmitted to the common complementary data lines CD1 and -CD1. Therefore, each complementary data line is recovered to a bias voltage VCD at high speed, and a data line of 'L' is quickly made to 'H'. |
