| 摘要 |
PURPOSE:To reduce an error of quantization by adding a constant 2L to the output of a digital filter when the number of taps of the digital filter is set at K with the arithmetic word length set at L bits respectively. CONSTITUTION:A constant generator 6 which produces a constant 2LK(1/2L) consisting of the number of taps K and the number of arithmetic bits L of a delay line 3 and an adder 7 which obtains the sum of the output Yi of an adder 5 and a constant K(1/2L) produced from the generator 6 and outputs it to a digital filter output terminal 2 are added to a conventional non-cyclic digital filter (1-dot chain line area). Then the signals supplied to the digital filter from an input terminal 1 are filtered by the line 3, coefficient multipliers 41-4k and the adder 5. This output signal Yi is added with the constant K(1/2L) and this sum Zi is outputted to the terminal 2.
|
