| 摘要 |
PURPOSE:To readily prevent a latchup phenomenon without conducting a parasitic transistor for forming a holding loop of a latchup by alternately disposing an N<+> type contacting region and a P<+> type contacting region between both MOS transistors. CONSTITUTION:P-channel MOS transistors 8, 9 having P<+> type sources, drain regions 2-5 and gate electrodes 6, 7 are formed on an N-type semiconductor substrate 1, N-channel MOS transistors 17, 18 having N<+> type sources, drain regions 11-14 and gate electrodes 15, 16 are formed on a P-type well region 10, N<+> type first contacting regions 19 and P<+> type second contacting regions 20 are alternately formed on the substrate 1 and the region 10 between the both transistors 8, 17 and 9, 18. The transistors 8, 17 and 9, 18 are aligned in parallel, the first N<+> type contacting region 19 is provided on the substrate 1 and the region 10 between the both source regions 2 and 11 of the first set of the transistors 8, 17 and P<+> type second contacting region 20 is provided between the both source regions 4 and 13 of the second set of the both transistors 9, 18. |
