发明名称 FIELD EFFECT TRANSISTOR LOGIC CIRCUIT
摘要 PURPOSE:To drive a buffer by one stage of an SCFL logic circuit by obtaining two inputs, 'true' and 'false' required for a totem pole type buffer from an output of the SCFL logic circuit. CONSTITUTION:An input signal voltage is impressed to a gate electrode 60 of an FET3 and a comparison voltage is impressed to a gate electrode 61 of an FET4. The difference between the input signal and the comparison voltage is amplified and appears output terminals 20, 21 of the SCFL. In general, the FETs 3, 4 are biased so as to be operated within a drain current saturation region. The outputs 20, 21 of the SCFL connect to the gate electrodes of FETs 6, 7 of the buffer circuit, one FET is turned on and the rest is turned off. Thus, an output is obtained from an output terminal 30.
申请公布号 JPS61186018(A) 申请公布日期 1986.08.19
申请号 JP19850025473 申请日期 1985.02.13
申请人 NEC CORP 发明人 MAETA TADASHI
分类号 H03K19/0952;H03K19/094 主分类号 H03K19/0952
代理机构 代理人
主权项
地址