| 摘要 |
A fast BCD/Binary Adder in which provision is made for selectively performing either binary or BCD arithmetic operations using an approach in which, for BCD addition, an appropriate correction value is always caused to be added to one of the input operands and an appropriate correction value conditionally subtracted from the result where required to give a proper BCD result. High speed operation is achieved by merging the binary input logic with the correction logic (10-13) so as to provide for addition of the correction value concurrently with the addition of the input operands in a manner which automatically takes into account any inter-bit carries that may be produced by the correction value. In addition, provision is made for concurrently producing conditional sums (one assuming the presence of an input carry and the other assuming the absence of a carry) in parallel with the performance of look-ahead carry operations (35). An output logical selection circuit (20-23) merges the selection logic for selecting the correct conditional sum (in response to the look-ahead carry produced) with the conditional subtraction logic required for BCD operation in a manner so that the two operations are performed concurrently during BCD operations. |
