| 摘要 |
In an error correcting apparatus, an add-compare-select circuit is provided for each state in a given time slot of a Viterbi trellis diagram. The ACS circuit includes first and second pairs of adders coupled to a source of sequentially updated path metrics and to a branch metric generator which generates sums of branch metrics over successive time slots. The updated path metrics of states two time slots prior to the given time slot and the branch metric sums are added up in the adders. The outputs of adders in pairs are compared respectively by first comparators to determine the highest of the adder outputs. The determined highest values are passed through first selectors to a second comparator to further determine the highest of the selected adder outputs, the further determined value being passed through a second selector to the path metric source to update the previous value. Control signals indicating the determinations taken by the first and second comparators are coupled to a path memory for storing data indicating the paths of the selected values.
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