| 摘要 |
PURPOSE:To make an input and output permitting signal continuous, and to execute the high speed processing by remaining a preliminary buffer for one step or preliminary data for one step and non-permitting the input and non- permitting the output before the storing condition of the data to a buffer goes to be full or empty. CONSTITUTION:At a first-in first-out buffer circuit, a data shift register DSR of (n) steps having data latch circuits B1-Bnm and an indication shift register LSR having data control circuits A1-An are provided. When data control information of a circuit A2 is off, the data control information of the circuit A3 is latched to FF1, and an input permitting signal IR2 is outputted by AND with the output of FF1 and the control information of the circuit 2 at a gate circuit 4. An output permitting signal OR2 is generated in accordance with the control information of circuits An-1 and An in the same way by an FF2, inverters 7 and 8 and a gate circuit 5, a signal OR2 is turned off by the logical output of the output of the circuit An and the output of an FF3, and the input and output permitting signals are made continuous.
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