发明名称 MULTI-INPUT EXCLUSIVE OR CIRCUIT
摘要 PURPOSE:To decrease the number of elements of a circuit itself and to reduce the stray capacity of a signal delay element by using one or plural two-input exclusive OR circuit composed of inverter circuits, a clocked gate circuit, and an analog switch circuit. CONSTITUTION:A two-input exclusive OR (NOR) circuit consists of inverter circuits 4 and 5 (204 and 205), a clocked gate circuit 6 (206), and an analog switch circuit 7 (207) and is equipped with input terminals 1 and 2 (101 and 102) and an output terminal 3 (203). In this case, 10 elements are used. This circuit is used to constitute a four-input exclusive OR circuit or eight-input exclusive OR circuit. The number of elements constituting the four-input exclusive OR circuit is 30 and the number of elements constituting the eight-input exclusive OR circuit is 70, so the number of elements of circuit configuration in this invention is less than before.
申请公布号 JPS61173521(A) 申请公布日期 1986.08.05
申请号 JP19850013846 申请日期 1985.01.28
申请人 SEIKO EPSON CORP 发明人 YOSHIZAWA MASAYUKI;TSUJI MASUO;KATSUNO KUNIO
分类号 H03K19/21 主分类号 H03K19/21
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