发明名称 ARITHMETIC CIRCUIT FOR MAJORITY VOTE
摘要 PURPOSE:To monitor whether or not an adder level is corresponding to the (n) number of levels, to detect a circuit trouble and to inform of the trouble without fail by clamping and adding successively the (n) number of input signals, and outputting the output of a majority vote when the adder level is corresponding to a (n/2)<(m) number of levels. CONSTITUTION:Rectifier circuits 21-23 are respectively to connected A-C system non-symmetrical error logic arithmetic originating device 11-13 of a majority vote arithmetic circuit, and rectifier outputs Va+Vb+Vc, in which an input signal is successively clamped and added, and outputted to a rectifier output terminal. A majority vote circuit 5 and a monitoring circuit 6 are connected to the output terminal, and the output level of the output terminal is monitored by the circuit 6. When the adder level of an (n) number of input signals are corresponding to the (n/2)<(m) levels, the majority vote output is outputted by the circuit 5, the circuit 6 monitors whether or not the adder level is corresponding to the (n) number of levels, and detects the circuit trouble and informs it without fail.
申请公布号 JPS61173348(A) 申请公布日期 1986.08.05
申请号 JP19850013855 申请日期 1985.01.28
申请人 NIPPON SIGNAL CO LTD:THE 发明人 KATO MASAKAZU;YOMOGIHARA KOICHI
分类号 G06F11/18 主分类号 G06F11/18
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