| 摘要 |
PURPOSE:To prevent a high-frequency output signal shifted remarkably from a normal frequency by stopping the operation of an output multiplier when a phase error at the outside of the permissible range at a phase locking detection circuit is detected. CONSTITUTION:When the phase locked circuit is normal, data outputted from the 1st digital comparator 11 remains at a range satisfying permissible phase error data stored in the 2nd register 12 and output data of a comparator 13 keeps the content of a prescribed phase locked loop. When the said phase synchronizing circuit is unlocked due to an external cause, the data outputted from the comparator 11 differs gradually from the content of the 1st register 10, and when the difference exceeds the content of the 2nd register 12, output data of the comparator 13 inverts the logic to stop the operation of the output multiplier 5 via a driver 14. Then a sweeper 7 is excited at the same time to acquire the phase locking again. When a fault takes place in the phase locked circuit in this way, an output of a high frequency signal shifted remarkably by the frequency than that at normal state is stopped to prevent interference with other communication device. |
