| 摘要 |
A chip carrier array (10) which includes interconnected chip carriers (11) separated from each other and from the substrate waste edge (25) by elongated slots (15) which define outer edges of the chip carriers (11). More particularly, each chip carrier (11) includes corners which are defined by elongated slots (15). Each chip carrier (11) includes a plurality of electrically isolated edge interconnects (19) which wrap around edges defined by the elongated slots (15). |
