发明名称 MANUFACTURE OF MATRIX ARRAY
摘要 <p>PURPOSE:To enable high breakdown voltage by a method wherein the upper layer of a first metallic layer is converted into a first insulator layer through a mask, the mask is removed, a second insulator layer, a semiconductor layer and a second metallic layer are formed and the second metallic layer is patterned. CONSTITUTION:A tantalum layer is shaped on a glass substrate 7 through sputtering in approximately 3,000Angstrom thickness, and patterned to form a gate bus line 8. A resist mask 9 is shaped so as to expose only a region in which the gate bus line 8 and a drain bus line will cross, and the upper section of the gate bus line is converted into a tantalum oxide (Ta2O3) layer 10 in approximately 1,000Angstrom thickness while using the gate bus line 8 as an anode. The used resist mask 9 is dissolved and removed, and a gate insulating film (SiO2) 11 and a hydrogenated amorphous silicon layer 12 are shaped on the whole surface of the substrate 7. Hydrogenated amorphous silicon layers 14 are formed through a plasma CVD method in which monosilane (SiH4) and phosphine (PH3) are used, aluminum films 15 are shaped continuously by employing a vacuum deposition method, and a source electrode-wiring 16 and a drain electrode-bus line 17 are formed.</p>
申请公布号 JPS60244071(A) 申请公布日期 1985.12.03
申请号 JP19840099943 申请日期 1984.05.18
申请人 FUJITSU KK 发明人 KAWAI SATORU;NASU YASUHIRO;YANAI KENICHI;INOUE ATSUSHI
分类号 G02F1/1343;G02F1/136;G02F1/1368;H01L21/3205;H01L27/12;H01L29/78;H01L29/786 主分类号 G02F1/1343
代理机构 代理人
主权项
地址