| 摘要 |
PURPOSE:To operate an adder with carry look-ahead at a slower operating timing while maintaining an operating speed and circuit simplicity, by statically performing the propagation of carry and, at the same time, making the propagating time of a logic '1' signal and that of a logic '0' signal the same. CONSTITUTION:When carry propagating signals P0-P3 are active with all bits by the action of gates 10a and 10b, low signal is inputted in a gate 10c and a high signal is inputted in a gate 10d. The output of the gate 10c always becomes a high level and the output of the gate 10d goes to -CIN, and then, a carry output COUT which is the output of a gate 10e goes to a carry input CIN. When all bits are not active, an output signal 6 implemented inside carry blocks 1-4 and propagated goes to the carry output COUT. Moreover, driving capacities for PMOS transistors 1d-4d of carry implementing and erasing circuits 1b-4b are made larger than those for NMOS transistors 1c-4c, so that the high signal can be propagated in the same propagating time as that for the low signal. |
