发明名称 MEMORY CONTROLLING SYSTEM OF DATA PROCESSOR
摘要 PURPOSE:To use effectively a prescribed logical memory space whose size is limited, by dividing the logical memory space into a common memory area and a bank memory area, and storing a common module and an individual module of a program, and only a bank control module in the bank memory area and the common memory area, respectively. CONSTITUTION:When assigning a memory, a common module 4 is provided in a bank memory area 2. In such a memory array, when executing a program, a main routine in a bank '0' is started first, and thereafter, individual modules 5-(n) are executed successively through a bank control module 3. Also, a call of the common module from the individual module is also executed through the bank control module 3. In this way, by storing the common module 4 in the bank memory area 2, a common memory area 1 can be reduced, and the bank memory area 2 is extended and widened, therefore, the storable quantity of the individual modules 5-(n) increases, and the utilizing efficiency of the memory becomes large.
申请公布号 JPS61165151(A) 申请公布日期 1986.07.25
申请号 JP19850006226 申请日期 1985.01.17
申请人 FUJITSU LTD 发明人 ANDO NORIYUKI;OGIWARA MIYUKI;MOTOHASHI YASUKO
分类号 G06F12/06 主分类号 G06F12/06
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