| 摘要 |
PURPOSE:To execute a subtraction cycle at a high speed by replacing a signal of AND and a signal of OR of the time of addition, with a signal which goes to a negative of OR of an input 1 and an inversion input 2, and a signal which goes to a negative of AND of the input 1 and the inversion input 2 of the time of subtraction. CONSTITUTION:At the time of addition, a signal which goes to AND of an input 1 and an input 2, and a signal which goes to OR of the input 1 and the input 2 are generated, and at the time of subtraction, a signal which goes to a negative of OR of the input 1 and the inversion input 2, and a signal which goes to a negative of AND of the input 1 and the inversion input 2 are generated by an intermediate sum generating circuit 6, and a carry foresight circuit 3, an internal carry generating circuit 4, and a final sum generating circuit 5 are used in common by a binary addition and subtraction processing, at the time of subtraction. In such a way, a subtraction cycle at the time of subtraction goes to all the same as the time of addition, and the subtraction cycle can be executed at a high speed. |
