| 摘要 |
PURPOSE:To improve the performance of the system, the profitability and reliability and to make the control of transmitting/receiving control information between a channel controller and a channel efficient by providing a 2-bit FF circuit at each channel. CONSTITUTION:The 2-bit FF circuit is provided in correspondence to each channel CHE4 to form a start request bit 30 and a receptionable bit 31. The bit 30 is controlled by channel controllers CHC1 and CHE4, which are brought into off-state at all times, and when the CHC1 starts a channel by an input/ output instruction, the CHC1 is set to on-state ahead the start. Further, the bit 31 is controlled by each CHE4, it is in on-state at all times, the CHE4 receives a request from an I/O and reset to an off-state prior to the start of the interruption request processing and into on-state when the processing is finished. The collision of transfer of control information between the CHC1 and the CHE4 is detected before the start of transfer by the provision of the bits 30, 31 in this way to establish the priority of processing thereby making the control efficient. |
