| 摘要 |
PURPOSE:To operate a data bus with 16 bits in a personal module by inserting an instruction selecting signal to a bus high enable signal. CONSTITUTION:The signal passing a buffer 21 and a control circuit 22 is latched in a latch circuit 23 and is stored in a sample memory 100 provided in a device body. The signal outputted from the control circuit 22 is led to a queue tracer circuit 24 also. Start byte detection signal EFIF and OFIF generated by the queue tracer circuit 24 are stored in the sample memory 100. |
