Digital polarity correlator

摘要

A self-testing facility is provided for a correlator comprising a delaying shift register (DSR) whose stages are respectively associated with a set of channels each incorporating a coincidence detector (G1+G2) and an integrating counter (IC), and a further shift register (OSR) which is used to inspect for the overload condition of the counters, the normal running condition involving application of binary signals respectively to the delaying shift register and to all the coincidence detectors. The operation of each channel is tested in a test mode involving inhibition of the normal running condition, and information indicative of faulty channels is recorded in a register (MCR); this information is used in the normal running condition to cause by-passing of those stages of the shift registers corresponding to faulty channels.