发明名称 VECTOR PROCESSOR
摘要 PURPOSE:To execute logical operation, four arithmetical operations, comparing operation, etc. in each vector element and to speed up the vector processing by setting an instruction code for specifying the kind of operation in each vector element and referring the instruction code. CONSTITUTION:An instruction code for specifying the kind of the operation is added to each element of a vector B. Addition '+' is used for respective instruction codes of elements B(1)-B(N-20) of the vector B and a subtraction '-'is used for respective instruction codes of elements B(N-19)-B(N). When data vectors of the vector B and the vector C are operated in each element, the arithmetic circuit adds the elements B(1)-B(N-20) of the vector B to the elements C(1)-C(N-20) of the vector C while referring to the instruction codes added to respective elements of the vector B and subtracts the elements B(N-19)-B(N) of the vector B from the elements C(N-19)-C(N) of the vector C also while referring to the instruction codes. The calculated results of the arithmetic circuit are stored as a vector A (result vector).
申请公布号 JPS61160176(A) 申请公布日期 1986.07.19
申请号 JP19840279655 申请日期 1984.12.29
申请人 HITACHI LTD 发明人 KINOSHITA YOSHIAKI;KAZAMA YOSHIHARU;MIYAMOTO SHUNSUKE;OMODA KOICHIRO;NAKAGAWA TAKAYUKI
分类号 G06F17/16;G06F15/78 主分类号 G06F17/16
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