| 摘要 |
PURPOSE:To reduce power consumption attened with sense operation and to speed up the sense operation by adopting the constitution that a sense amplifier activating signal transited from an intermediate potential into a common potential or a power supply potential is outputted while a sense part signal is received. CONSTITUTION:A bit line precharge signal phiPC is activated in synchronizing with an RAS precharge period. An intermediate potential precharge circuit 1 is formed with an intermediate potential precharge transistor (TR) N3 whose gate is drive by the precharge signal phiPC and N-channel MOSTRs N4, N5 for intermediate potential application applying an intermediate potential to bit lines BL, BL during the RAS precharge period to keep the bit line pair at the intermediate potential. A sense amplifier drive circuit 2 receiving a sense start signal during the RAS active period and outputting sense amplifier activating signals phiSEN, phiSEP outputs the phiSEN signal transited from the intermediate potential to a VSS level and the phiSEP signal transited from the intermediate potential to a VCC power supply level with a delay from the approx.=SEN signal.
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