| 摘要 |
PURPOSE:To obtain the titled circuit from which high electrostatic break-down strength and high latch-up strength to input surge can be obtained, by surrounding the first and second clamp diodes each by specific diffusion regions. CONSTITUTION:This input protection circuit for CMOS transistor FETs 1, 2 consists of clamp diodes D1, D2 and a resistor R1 connected between the diodes D1, D2 and the gate terminal. When a positive or negative overvoltage is impressed on the input V1, the diodes D1, D2 set in action and avoid the concentration of the power of input overvoltage to the resistor R1. The diode D1 is surrounded by a P-island connected to Vss, and the island where the diode D2 is formed is surrounded by an N-type diffused layer connected to a power source Vdd, thereby forming transistors Tr5, Tr4. These transistors Tr5, Tr4 improve the latch-up strength to positive-negative directional surge by the difficulty of flowing the base currents of the transistors Tr2, Tr1. |
