| 摘要 |
PURPOSE:To enable the inhibition of latch-up phenomenon without decreasing high-speed action and rain withstand voltage, by providing an impurity region under the source region. CONSTITUTION:This well CMOS inverter is provided with an N-well 22 in the surface of a P-type Si substrate 21, a P<+> type source region 26 in its surface, and an N<+> type impurity region 41 serving as the contact region with the N-well 22 thereunder. The surface of the substrate 21 except the N-well 22 is provided with an N<+> type source region 28, and a P<+> type impurity region 40 serving as the contact region with the substrate 21 is provided thereunder. This construction keeps the base resistance of a lateral parasitic transistor much smaller, because of the impurity region 40 provided under the source region 28, even when large negative voltage pulses are impressed on a wiring electrode wiring 45 and makes this parasitic transistor up difficult to turn ON. Therefore, the latch-up phenomenon can be inhibited. |
