| 摘要 |
PURPOSE:To decrease an internal flip-flop circuit by providing a function generating a decode waveform to a part counting a high-order bit of a frequency division circuit so as to incorporate the frequency division section and the decode section in a decode counter frequency-dividing a clock signal to obtain a desired decode waveform output. CONSTITUTION:Taking Qa, Qb as 00 for example, when a clock signal is inputted from a clock input terminal 38 after initializing, the flip-flop circuit group starts count-up and a signal of a signal line 13 rises after 9 counts. Further, the signal of the signal line 13 rises at each 32-count of the clock input and at least one state of flip-flop circuits 9-6 is changed. The level of the signal on the signal line 12 goes to H and the output of an NOT circuit 37 goes to L when the Q output of the flip-flop circuit 10 goes to H. A frequency division output of a frequency division number of 1/201 is obtained to the signal line 12 by repeating the operation above.
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