发明名称 TRANSMISSION BUFFER MEMORY
摘要 <p>PURPOSE:To prevent duplicated write of data or missing of write by monitoring at all time the phase difference between the write address and the read address, subtracting 2pi from theta0 when the phase difference exceeds 16pi, and adding theta0 by 2pi when the phase difference goes to negative. CONSTITUTION:The output 141 of a detection circuit 30 becomes '1' when the phase difference between the write address and the read address becomes negative or exceeds 16, but otherwise is '0'. The A>B output 142 becomes '1' when the phase difference is negative, but becomes '0' when the difference exceeds 16pi. The outputs 141 and 142, as a phase-relation information, is inputted respectively to the clock terminal and the U/D terminal of an up-down counter 14. Therefore, when the phase difference between the write address and the read address becomes negative, the said counter 14 counts up by 1, and counts down by 1 when the difference exceeds 16pi. In result, correction of duplication or missing of writing in the buffer memory and setting an optimum threshold value is set automatically.</p>
申请公布号 JPS61156933(A) 申请公布日期 1986.07.16
申请号 JP19840277385 申请日期 1984.12.27
申请人 NEC CORP 发明人 SUZUKI HIDEHIKO
分类号 H04J3/07;H04J3/06;H04L7/00;H04L13/08 主分类号 H04J3/07
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