| 摘要 |
PURPOSE:To realize a low speed frame synchronization restoring circuit even when a loop control time of a shift loop exceeds one clock time of low order group by using a 1-bit delay shift system as a parallel detection type low order group 1-bit shift system in a high speed PCM frame synchronization. CONSTITUTION:A serial converting circuit 1 outputs a 4-bit parallel signal from a high order group signal Si. A synchronizing pattern detection circuit 2 compares a 4-bit parallel utput (inverted output Q) from the serial/parallel converting circuit 1 with frame synchronizing pattern signals R1-R4 applied from a frame counter 3, and when they are not coincident, an output of an NOR gate 24 goes to logical 0 and an output of an NOR gate 25 goes to logical 1. A delay circuit 5 outputs an output of the gate 25 until the detection of next synchronizing pattern, blocks one bit of a high order group clock signal inputted to a 1/4 frequency division circuit and then the point of time of synchronizing patter is delayed by one bit. The operation is repeated, and when the R1-R4 and a 4-bit parallel output from the serial/parallel converting circuit 1 are coincident, the synchronization is established, the output of the gate 24 goes to logical 1 and the output of the gate 25 goes to logical 0. |
