| 摘要 |
PURPOSE:To decrease the delay in a signal of a specific channel by extracting a signal of specific channel separately, inserting the signal to a time slot of the said specific channel of an optional frame of an output multi-frame signal and transmitting the result. CONSTITUTION:An input multi-frame signal 20 is written sequentially in a storage circuit 2 by using an input clock 22 synchronously with an input multi- frame pulse 21. The specific channel signal, e.g., the signal of the channel 1 is extracted separately by a channel separation circuit 3 and written sequentially in a bit phase synchronizing circuit 4 as shown in figure D by using the input clock 22. Signals (B0-B7) of the channel 1 of a frame F0 written in the bit phase synchronizing circuit 4 are read by using an output clock 25 at a time slot of the channel 1 of an optional frame, e.g., a frame F1 of the output multi- frame signal 23 read from the storage circuit 2, inputted to a channel inserting circuit 5, which inserts an output signal of the bit phase synchronizing circuit 4 to a time slot of the channel 1 of a frame F1 of the output multi-frame signal outputted from the storage circuit 2. |
