发明名称 MULTIPLIER CIRCUIT
摘要 PURPOSE:To reduce the leakage of an input signal to the output side by preventing input of the signal to the base of a transistor for comprising the 3rd differential pair when one of transistors for comprising the 1st differential pair is turned on and the other is turned off. CONSTITUTION:The 1st and 2nd input signals of transistors 501 and 502 are inputted to the input terminals 1 and 2 of a differential pair composed of transistors 401 and 402. The 3rd and fourth input signals of terminals 503 and 504 are inputted to the input terminals 3 and 4 of differential pairs 101, 105 and 106 constituted of transistors 5 and 6, transistors 403 and 404 and those of 405 and 406, respectively. Then a signal at a point 413, that at a point 414, that at a point 415 and that at a point 416 become as codes 513, 514, 515 and 516 show, respectively, and the output signals of output terminals 14 and 15 output signals of satisfactory phases as codes 524 and 525 show, respectively. Accordingly, when the TR5 and TR6 for comprising the 1st differential pair are turned on and off, respectively, the signal is not inputted to the base terminals of transistors TR9 and TR10 for comprising the 3rd differential pair, thereby reducing a crosstalk between the input and output.
申请公布号 JPS61152107(A) 申请公布日期 1986.07.10
申请号 JP19840272976 申请日期 1984.12.26
申请人 HITACHI LTD 发明人 OSAKA ICHIRO;AKITAKE ISAO;HORI KAZUAKI
分类号 H03D3/02;H03D13/00 主分类号 H03D3/02
代理机构 代理人
主权项
地址