发明名称 Analog switch circuit having output offset compensation circuit
摘要 An analog switch circuit which is provided with a transmission gate consisting of a first n channel MOS transistor and a first p channel MOS transistor, which transistors are connected in parallel, wherein the output terminal of said transmission gate is connected to a second n channel MOS transistor and a second p channel MOS transistor, which transistors are supplied with an output voltage Vout from the transmission gate, and wherein mirror capacitances CmP12, CmP13, CmN12, CmN13 are provided at the output terminal of the transmission gate to offset a difference between the mirror capacitance CmN11 of the first n channel MOS transistor and the mirror capacitance CmP11 of the first p channel MOS transistor.
申请公布号 US4599522(A) 申请公布日期 1986.07.08
申请号 US19830552791 申请日期 1983.11.17
申请人 TOKYO SHIBAURA DENKI KABUSHIKI KAISHA 发明人 MATSUO, KENJI;TANAKA, FUMINARI
分类号 H03K17/06;H03K17/16;H03K17/687;(IPC1-7):H03K17/16 主分类号 H03K17/06
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