| 摘要 |
<p>PURPOSE:To initialize a device in a short time by reading data in memory only through one first cycle and iterating only a memory write cycle afterwards. CONSTITUTION:A direct memory access controller DMAC outputs the high order (Ahs) of a source address to a system data bus DB in the first half of the initial transfer cycles (T1-Sr), further outputs an address strobe signal STB and holds it in a latch 11. The DMAC outputs the low order (Als) of the source address and a memory read signal MR in the latter half of the cycles T1-Sr, and fetches contents D at addresses of the (Ahs and Als) in memory into a temporary register TEMP. The DMAC holds the high order (Ahd) of a destination address in the latch 11 in the first half of the next cycles (T1-Sw), while in the latter half the DMAC outputs the low order (Ald) of said address and a memory write signal MW, and writes the data D of the temporary register TEMP at the addresses (Ahd and Ald). Afterwards the write cycle is repeated up to the final address by advancing the destination address one by one.</p> |
