发明名称 LOGICAL VALUE CONVERTING CIRCUIT
摘要 PURPOSE:To apply logical conversion without decreasing the effect of an indefinite value by outputting a value of a logical value setting circuit possible for being set optionally when the logical state of two input signal lines is indefinite so as to convert the indefinite value of logical simulation into a fixed value. CONSTITUTION:The input signal lines 101, 102 represents 2-bit, that is, one logical state by two lines, and in taking the state when the signal line 101 is logical 0 and the signal line 102 is logical 1 as an indefinite value, an indefinite value detection circuit 103 brings the level of a control signal line 104 to logical 1 when the level of the signal line 101 is logical 0 and when the level of the signal line 102 is logical 1. A logical value setting circuit 105 outputs a set 0 or 1 to a logical value display lines 106. A selection circuit 108 produces the value of the logical value display line 106 to an output signal line 107 when the level of the control signal line 104 is logical 1 and produces the value of the input signal line 101 to the output signal line 107 when the value is logical 0.
申请公布号 JPS61147349(A) 申请公布日期 1986.07.05
申请号 JP19840267449 申请日期 1984.12.20
申请人 NEC CORP 发明人 KATO SHUNICHI
分类号 G06F11/25;G06F11/26;G06F17/50 主分类号 G06F11/25
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