| 摘要 |
PURPOSE:To clamp a signal line at a reference potential with a low impedance even if the wiring resistance of a word line is increased, by providing plural clamping circuits on the same signal line. CONSTITUTION:When a signal S is applied (to secure a high level) in case a NOR circuit is selected, i.e., a high level is kept at a node NO, the output CL of a NAND circuit is set at a low level. Thus clamping transistors TRT10-T12 are all turned off. Then a word line is selected and set at a high level with application of a signal PR. When such timing is set to apply both signals S and PR at a time, the TRT10-T12 are turned off earlier than the start of the rise of the word line in case the NOR circuit is selected. Thus the rise speed of the word line is not delayed. As a result, no delay is produced even if the levels of TRT10-T12 are increased together with the word line clamped at a reference potential with a lower impedance since those TRT10-T12 are turned off before application of the signal PR. |
